In the field of high speed computer processors, there have been a variety of approaches to the problem of how best to encode instructions. Early on, processors manufactured by Intel.RTM. Corporation utilized variable length encoding in which different instruction were encoded with different bit lengths. While this approach gained wide acceptance in the computer industry, the Intel architecture (iA) encoding method was improved on by reduced instruction set computing (RISC) machines.
In a RISC machine, all fields are uniformly encoded, with every instruction having a fixed length (e.g., 32-bits). The fixed, 32-bit length of the instruction fields provide enough bit positions, or "space", to encode instructions that use three operands, with every operand containing a 5-bit register identification. Therefore, the RISC approach provides adequate space to encode opcode bits, immediate values, offsets, etc.
More recently, there has developed a demand in the computer industry for highly efficient, parallel processing machines having the ability to process a large plurality of instructions in a single machine cycle. These machines, commonly referred to as very long instruction word (VLIW) or wide-word computer processors, are capable of processing several instructions at a time. By way of example, a VLIW multiprocessor capable of handling 1,024-bits of instruction each clock cycle is described in U.S. Pat. No. 4,833,599.
One of the problems that arises in a VLIW or wide-word machine is how to encode instructions which address large register files, i.e., 128 registers. One approach, adopted by Hewlett-Packard.RTM., Co., in their original wide-word designs was to group instructions in a single 128-bit entry that contained three 42-bit instructions (with 2 bits leftover). Each of the three instructions of the 128-bit entry was restricted to be of a certain type. That is, the first instruction is restricted to being a memory type instruction, the second instruction had to be an integer type, and the third instruction was limited to being a floating-point type of instruction.
The fundamental problem with this wide-word, fixed, 128-bit format is that it greatly expands the code and introduces inefficiencies in the packing of instruction bytes. For example, a LOAD instruction may only be 1 or 2 bytes long, but in prior art wide-word format, 42-bits would necessarily still be supplied. Even greater inefficiencies arise in sequences of instructions where only 1 or 2 of the instructions in each of the successive 128-bit instruction entries are utilized.
Persons familiar with superscalar processors will further appreciate that RISC machines also suffer difficulties when trying to simultaneously process a large number of instructions. For example, a RISC processor designed to execute many instructions in parallel requires an large number of multiplexers and associated wiring to route the various instructions to the appropriate functional units. This places practical limitations on the number of instructions which can be processed in parallel.
Thus, there is a need for a processor that reduces the waste and inefficiency associated with past instruction encoding methods and apparatus. As will be seen, the present invention provides a processor capable of simultaneously executing a plurality of sequential instructions with a highly-efficient encoding of instructions.